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mp1230a/31a/32a 1 rev. 2.00 features ? superior ruggedized 1230 series: 2 kv esd ? four quadrant multiplication ? stable, more accurate segmented dac approach 0.2 ppm/ c linearity tempco 2 ppm/ c max gain error tempco lowest sensitivity to amplifier offset lowest output capacitance (c out = 80pf) lower glitch energy ? monotonic over temperature range cmos microprocessor compatible double-buffered 12-bit digital-to-analog converter ? lower data bus feedthrough @ cs = 1 ? v dd from +11 v to +16 v ? latch-up free cmos technology ? 12-bit bus version: mp1208/1209/1210 ? 16-bit upgrade: mp7636a general description the mp1230a series are superior pin for pin replacements for the 1230 series. the mp1230a series is manufactured using advanced thin film resistors on a double metal cmos process which promotes significant improvements in reliability, latch-up free performance and esd protection. the mp1230a series incorporates a unique decoding tech- nique yielding lower glitch, higher speed and excellent accuracy over temperature and time. 12-bit linearity is achieved without trimming. outstanding features include: stability: integral and differential linearity tempcos are rated at 0.2 ppm/ c typical. monotonicity is guaranteed over all temperature ranges. scale factor tempco is a low 2 ppm/ c maximum. low output capacitance: due to smaller mosfet switch geometries allowed by decoding, the output capacitance at i out1 and i out2 is a low 80pf / 40pf and 25pf / 65 pf. this less than half the competitive dac 1230 series. lower ca- pacitance allows the mp1230a series to achieve settling times faster than 1 m s for a 10 v step. low sensitivity to output amplifier offset: the linearity er- ror caused by amplifier offset is reduced by a factor of 2 in the mp1230a series over conventional r-2r dacs. the mp1230a series uses a circuit which reduces transients in the supplies caused by data bus transitions at cs = 1. simplified block diagram dgnd 12 dq dq db11-db4 db3-db0 dq agnd 12 8 4 4 8 8 input latch dac latch v dd v ref r fb i out1 i out2 v ref byte1/byte2 cs wr1 xfer wr2 le le le
mp1230a/31a/32a 2 rev. 2.00 ordering information package type temperature range part no. plastic dip plastic dip plastic dip 40 to +85 c 40 to +85 c 40 to +85 c + 1/2 + 3/4 + 1+ 1 + 2+ 2 + 0.4 + 0.4 + 0.4 mp1230abn MP1231Abn mp1232abn soic mp1230abs 40 to +85 c soic MP1231Abs 40 to +85 c soic mp1232abs 40 to +85 c + 1/2 + 3/4 + 0.4 + 1+ 1+ 0.4 + 2+ 2+ 0.4 inl (lsb) dnl (lsb) gain error (% fsr) pin configurations 20 pin pdip (0.300o) n20 agnd dgnd db7 db6 db5 db4 20 1 11 10 2 3 4 5 6 7 15 14 13 12 17 16 8 9 19 18 20 pin soic (jedec, 0.300o) s20 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v dd i out2 i out1 r fb v ref db8 (db0, lsb) db9 (db1) db10 (db2) db11 msb (db3) v dd i out2 i out1 db8 (db0, lsb) db9 (db1) db10 (db2) db11 msb (db3) agnd dgnd db7 db6 db5 db4 r fb v ref see packaging section for package dimensions byte1/byte2 cs wr1 xfer wr2 byte1/byte2 xfer wr2 cs wr1 pin out definitions 1cs chip select (active low) 2 wr1 write 1 (active low) 3 agnd analog ground 4 db7 data input bit 7 5 db6 data input bit 6 6 db5 data input bit 5 7 db4 data input bit 4 8v ref reference input voltage 9r fb feedback resistor 10 dgnd digital ground 11 i out1 current output 1 pin no. name description 12 i out2 current output 2 13 db11 (db3) data input bit 11 (msb) data input bit 3 14 db10 (db2) data input bit 10 data input bit 2 15 db9 (db1) data input bit 9 data input bit 1 16 db8 (db0) data input bit 8 data input bit 0 (lsb) 17 xfer transfer control signal (active low) 18 wr2 write 2 (active low) 19 byte1/ byte sequence control byte2 20 v dd positive power supply pin no. name description
mp1230a/31a/32a 3 rev. 2.00 electrical characteristics (v dd = + 15 v, v ref = +10 v unless otherwise noted) 25 c tmin to tmax parameter symbol min typ max min max units test conditions/comments static performance 1 fsr = full scale range resolution (all grades) n 12 12 bits integral non-linearity inl lsb best fit straight line spec. (relative accuracy) (max inl min inl) / 2 mp1230abn/atd/abs + 1/2 + 1/2 MP1231Abn/atd/abs + 1+ 1 mp1232abn/atd/abs + 2+ 2 differential non-linearity dnl lsb mp1230abn/atd/abs + 3/4 + 3/4 MP1231Abn/atd/abs + 1+ 1 mp1232abn/atd/abs + 2+ 2 gain error ge + 0.4 + 0.4 % fsr using internal r fb gain temperature coefficient 2 tc ge 0.5 + 2 ppm/ c d gain/ d temperature power supply rejection ratio psrr 5 + 20 + 20 ppm/% |d gain/ d v dd | d v dd = + 0.25v output leakage current i out 1+ 10 + 200 na dynamic performance 2 r l =100 w , c l =13pf current settling time t s 1.0 m sec full scale change to 1/2 lsb ac feedthrough at i out1 f t 1.0 mv p-p v ref =100khz, 20vp-p, sinewave reference input input resistance r in 5 10 20 5 20 k w digital inputs logical a1o voltage v ih 3.0 2.4 3.0 v logical a0o voltage v il 0.8 0.8 v input leakage current i lkg + 1+ 1 m av in = 0, 5 v input capacitance 2 10 pf analog outputs 2 output capacitance c out1 80 100 100 pf dac inputs all 1's c out1 40 60 60 pf dac inputs all 0's c out2 65 85 85 pf dac inputs all 1's c out2 25 45 45 pf dac inputs all 0's power supply functional voltage range 4 v dd +4.5 +16 +4.5 +16 v supply current i dd 1.2 2.0 2.0 ma all digital inputs = 0 v or all = 5 v
mp1230a/31a/32a 4 rev. 2.00 25 c notes: parameter symbol min typ max min max units test conditions/comments switching characteristics 2, 3 chip select to write set-up time t cs 200 100 ns chip select to write hold time t ch 10 0 ns data valid to write set-up time t ds 100 50 ns data valid to write hold time t dh 90 70 ns write pulse width, t wr 100 50 ns specifications are subject to change without notice electrical characteristics (cont'd) tmin to tmax 1 full scale range (fsr) is 10v. 2 guaranteed but not production tested. 3 see timing diagram. 4 specified values guarantee functionality. refer to other parameters for accuracy. absolute maximum ratings (t a = +25 c unless otherwise noted) 1, 2 v dd to gnd +17 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital input voltage to gnd gnd 0.5 to v dd +0.5 v . . . . i out1 , i out2 to gnd gnd 0.5 to +6.5 v . . . . . . . . . . . . . . . . v ref to gnd + 25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v rfb to gnd + 25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . agnd to dgnd + 1 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (functionality guaranteed + 0.5 v) storage temperature 65 c to +150 c . . . . . . . . . . . . . . . . . lead temperature (soldering, 10 seconds) +300 c . . . . . . package power dissipation rating to 75 c cdip, pdip, soic 900mw . . . . . . . . . . . . . . . . . . . . . . . . . derates above 75 c 12mw/ c . . . . . . . . . . . . . . . . . . . . . notes: 1 stresses above those listed under aabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only and functional operation at or above this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 2 any input pin which can see a value outside the absolute maximum ratings should be protected by schottky diode clamps (hp5082-2835) from input pin to the supplies. all inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100ma for less than 100 m s. 3 gnd refers to agnd and dgnd.
mp1230a/31a/32a 5 rev. 2.00 timing diagram t ch 50% 50% 50% 50% 50% 50% settled to + 0.01% cs , byte1/byte2 wr data bits t cs t wr t ds t dh v ih v il v ih v il v ih v il i out1 , i out2 t s definition of control signals: cs : chip select.(active low) it will enable wr1 . wr1 : write 1 (active low) the wr1 is used to load the digital data bits (db) into the input latch. byte1/byte2 : byte sequence control. the byte1/byte2 control pin is used to select both msb and lsb input latches. wr2 : write 2 (active low) it will enable xfer . xfer : transfer control signal (active low) this signal in combination with wr2 causes the 16-bit data which is available in the input latches to transfer to the dac register db0 to db11: digital inputs. db0 is the least significant digital input (lsb) and db11 is the most significant digital input (msb). i out1 : dac current output 1 bus. i out1 is a maximum for a digital code of all 1's in the dac register, and is zero for all 0's in the dac register. i out2 : dac current output 2 bus. i out2 is a complement of i out1 . r fb : feedback resistor. this internal feedback resistor should always be used (not an external resistor) since it matches the resistors in the dac and tracks these resistors over tempera- ture. v ref : reference voltage input. this input connects an external precision voltage source to the internal dac. the v ref can be selected over the range of +25v to 25v or the analog signal for a 4-quadrant multiplying mode application. v dd : power supply voltage. this is the power supply pin for the part. the v dd can be from +5 v dc to +15 v dc, however optimum volt- age is +12 to +15 v dc. agnd: analog ground back gate of the dac n-channel current steering switches. dgnd: digital ground
mp1230a/31a/32a 6 rev. 2.00 theory of operation figure 1. functional diagram d d d d d d d d q q q q q q q q d d d d d d d d q q q q q q q q d d d d q q q q d d d d q q q q msb lsb 8-bit input latch 4-bit input latch 12-bit dac register 12-bit multiplying d/a converter byte1/byte2 cs wr1 xfer wr2 dgnd agnd le le le when le = 1, q outputs follow d inputs when le = 0, q outputs are latched v dd v ref r fb i out1 i out2 db11 (msb) (db3) db10 (db2) db9 (db1) db8 (db0) db7 db6 db5 db4 digital interface figure 1. shows the internal control logic that controls the writing of the input latches. it is easy to understand how the mp1230a/31a/32a works by understanding each basic opera- tion. writing to input latches the condition byte1/byte2 = high, cs = wr1 = 0 loads the data bus db11-db4 into both input latches. a second cycle with byte1/byte2 = low ( figure 2. ) loads the pins db11-db8 (db3-db0) into the 4-bit input latch. timing diagrams show the inputs cs and db11-db0 to be stable during the entire writing cycle. in reality all the above sig- nals can change ( figure 2. ) as long as they meet the timing con- ditions specified in the electrical characteristic table. figure 2. write cycles to input latches wr1 cs byte1/byte2 data transferring data to the dac latches once one or all the input latches have been loaded, the condi- tion xfer = wr2 = low transfers the content of the input latches in the dac latch. the outputs of the dac latch change and the dac current (i out ) will reach a new stable value within the set- tling time t s ( figure 3. ). wr2 xfer db11-0 t s figure 3. transfer cycles from input latches to dac latches or or i out
mp1230a/31a/32a 7 rev. 2.00 performance characteristics graph 1. relative accuracy vs. digital code application notes refer to section 8 for applications information
mp1230a/31a/32a 8 rev. 2.00 symbol min max min max a 0.097 0.104 2.464 2.642 a 1 0.0050 0.0115 0.127 0.292 b 0.014 0.019 0.356 0.483 c 0.0091 0.0125 0.231 0.318 d 0.500 0.510 12.70 12.95 e 0.292 0.299 7.42 7.59 e 0.050 bsc 1.27 bsc h 0.400 0.410 10.16 10.41 h 0.010 0.016 0.254 0.406 l 0.016 0.035 0.406 0.889 a 0 8 0 8 inches millimeters e 20 11 20 lead small outline (300 mil jedec soic) s20 10 d e h b a l c a 1 seating plane a h x 45
mp1230a/31a/32a 9 rev. 2.00 20 lead plastic dual-in-line (300 mil pdip) n20 20 1 11 10 d eb 1 a 1 e 1 a c e a l b q 1 seating plane symbol min max min max inches a 0.200 5.08 a 1 0.015 0.38 b 0.014 0.023 0.356 0.584 b 1 (1) 0.038 0.065 0.965 1.65 c 0.008 0.015 0.203 0.381 d 0.945 1.060 24.0 26.92 e 0.295 0.325 7.49 8.26 e 1 0.220 0.310 5.59 7.87 e 0.100 bsc 2.54 bsc l 0.115 0.150 2.92 3.81 a 0 15 0 15 q 1 0.055 0.070 1.40 1.78 s 0.040 0.080 1.02 2.03 millimeters s note: (1) the minimum limit for dimensions b1 may be 0.023o (0.58 mm) for all four corner leads only.
mp1230a/31a/32a 10 rev. 2.00 notes
mp1230a/31a/32a 11 rev. 2.00 notes
mp1230a/31a/32a 12 rev. 2.00 notice exar corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contains here in are only for illustration purposes and may vary depending upon a user's specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circum- stances. copyright exar corporation datasheet april 1995 reproduction, in part or whole, without the prior written consent of exar corporation is prohibited.

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